Method and circuit arrangement for detecting synchronization patterns in a receiver

ABSTRACT

To provide a method and a circuit arrangement ( 100 ) for detecting synchronization patterns in a receiver, particularly in a UHF receiver or a VHF receiver, by which the average current consumption in a system with a receiver, particularly a UHF receiver or a VHF receiver, and with a subsequently arranged controller unit ( 200 ) can be clearly reduced,  
     at least a shift register ( 30 ) whose input can be impressed with an incoming signal and which is provided for picking up or taking over the signal state pattern particularly determined by the slopes;  
     at least a slope detector ( 40 ) whose input can also be impressed with the incoming signal;  
     at least a clock recovery unit ( 50 ) to be synchronized with the signal and preceded by the slope detector ( 40 ), the output of said clock recovery unit being connected to the clock input ( 30   c ) of the shift register ( 30 ); and  
     at least a decision unit ( 60 ) preceded by the shift register ( 30 ) for comparing, particularly continuously comparing the signal state pattern picked up by the shift register ( 30 ) and possibly also completely inverted with a predetermined state pattern stored in at least a pattern memory ( 70 ) assigned to the decision unit ( 60 ) are provided.

[0001] The present invention relates to a method and a circuitarrangement for detecting synchronization patterns in a receiver,particularly a UHF receiver (UHF=ultra high frequency) or a VHF receiver(VHF=very high frequency).

[0002] In a multitude of radio systems currently used on a UHF or VHFbasis, the high-frequency signal picked up by an antenna is applied to aUHF receiver or a VHF receiver in conformity with the receptionbandwidth and the reception frequency. The demodulated and digitizedlow-frequency signal is passed on via a data output to a connectedcontroller unit, particularly a microcontroller unit, for furtherprocessing.

[0003] The decision whether the demodulated and digitized signal is avalid data signal or only digital noise is entirely taken by thecontroller unit in these conventional systems. In this respect, it is tobe noted that a multitude of transmission units having the same carrierfrequency is used in the frequency range of the ISM bands so that thecontroller unit receives a multitude of additional signals which do notoriginate from the desired transmission unit at all.

[0004] The above-described conventional systems have in common that,fundamentally, both system components, i.e. both the UHF or VHF receiverand the controller unit must be permanently or at least predominantlyoperative for the reasons mentioned above. This fact is particularly adrawback in those conventional systems in which a low average currentconsumption is required, for example, in battery-operated conditions.

[0005] It is an object of the invention to provide a method and acircuit arrangement of the type described in the opening paragraph bywhich the average current consumption in a system with a receiver,particularly a UHF receiver or a VHF receiver, and with a subsequentlyarranged controller unit can be clearly reduced.

[0006] This object is achieved by a method as defined in claim 1 and bya circuit arrangement as defined in claim 11. Advantageous embodimentsand further implementations of the present invention are defined in thedependent claims.

[0007] In accordance with the teaching of the present invention, asignificant reduction of the average current consumption can be achievedin that the received demodulated signal is evaluated by the receiver,particularly the UHF receiver or VHF receiver so that the controllerunit can remain in a current-saving standby or sleep mode when thesignal is received. The controller unit is only impressed with thesignal and thereby further switched on when the receiver detects a givenpattern, particularly a synchronization pattern, in the demodulatedsignal and thus concludes that there is a valid data signal rather thanfor example, only digital noise.

[0008] In contrast to the circuit arrangements already known (cf., forexample, the prior-art U.S. Pat. Nos. 4,194,153; 4,745,408 or5,428,820), the present invention utilizes the fact that the protocolsof most radio broadcast systems have synchronization patterns which areset before the start of each data signal and are used for distinguishingvalid data signals from digital noise and/or for detecting whether thereceived data signal originates from the desired transmission unit.

[0009] In accordance with an advantageous embodiment of the presentinvention, the data clock generated by the clock recovery unit is notapplied to an output assigned to the data clock until after the signalstate pattern picked up by the shift register and possibly alsocompletely inverted is compared with the predetermined state pattern,for example, by way of an AND combination with the decision signaloriginating from the decision unit.

[0010] Independently thereof, or in addition thereto, it is notnecessary that the controller unit is switched on again through a dataline preceded by the AND circuit when a valid data pattern or statepattern is detected, but may also be effected through another controlline, for example, through a data clock line subsequent to the clockrecovery unit.

[0011] In connection with the subject matter of the present invention itshould be noted that the shift register plays an essential role both inthe method and in the circuit arrangement according to the invention.The shift register is essentially a serial information memory which maycomprise a plurality of serially arranged memory cells, for exampleflipflops, with each memory cell being generally capable of storing abit.

[0012] The information contents of each memory cell can be essentiallyshifted from memory cell to memory cell by the clock signal, i.e. fromthe input of the shift register to the output of the shift register. Dueto the serial input, there is direct access only to the first memorycell in the chain in the shift register so that the time of access tothe information is larger than, for example, in a parallel register.

[0013] The shift register is preferably formed as a switching circuitfor which, for example, the CCD technique (CCD=charge-coupled device) issuitable for realizing very long shift registers up to 64 kbit.

[0014] The present invention also relates to an integrated circuit,particularly a controller unit controlled by at least a circuitarrangement as described hereinbefore.

[0015] These and other aspects of the invention are apparent from andwill be elucidated with reference to the embodiments describedhereinafter.

[0016] In the drawings:

[0017]FIG. 1 shows diagrammatically an embodiment of a circuitarrangement according to the invention;

[0018]FIG. 2 shows a diagram in which the storage of state patterns andthe resultant synchronization patterns are illustrated; and

[0019]FIG. 3 shows a diagram in which the clock recovery by means of theclock recovery unit for the shift register is plotted against time.

[0020] The circuit arrangement 100 shown in FIG. 1 is adapted to detectsynchronization patterns (an 8-bit synchronization pattern in thisembodiment; cf. FIG. 2) in a UHF receiver or a VHF receiver.

[0021] A digitized signal picked up by an antenna (not shown in FIGS. 1to 3 for reasons of clarity) demodulated by a demodulator 10 is receivedby the D input 20 d of a first D(elay)-flipflop unit 20, synchronizedwith a clock signal received by the clock input 20 c of the firstD-flipflop unit 20 and applied to the input of a shift register 30.

[0022] The length of the shift register 30 is determined by the lengthof the signal state pattern to be detected (a 16-bit state pattern inthis embodiment; cf. FIG. 2). The instantaneous state of the signal istaken over in the shift register 30 upon each slope generated by theclock recovery unit 50.

[0023] It should be noted with respect to FIG. 2 that each data bit inthe synchronization pattern is described by two consecutive states (“0”or “1”, or “low” or “high”) and stored in a pattern memory 70 (cf. FIG.1). Since the overall depth of the pattern memory 70 is larger by afactor of 2 than the number of bits of the synchronization pattern, a16-bit state pattern is obtained.

[0024] The stored states of the shift register 30 are now continuouslycompared with the defined, predetermined values of the pattern memory70. Only when the signal state pattern picked up by the shift register30 and possibly also completely inverted entirely corresponds to thestate pattern in pattern memory 70 is the signal enabled for furtherprocessing in a controller unit 200 (cf. FIG. 1). In this case, the dataclock generated by the clock recovery unit 50 can also be used by thesubsequent circuit, for example, by the subsequent controller unit 200.

[0025] Particularly for the release of the signal, a decision unit 60 isarranged for further processing in the controller unit 200 between theshift register 30 and the pattern memory 70, which decision unit isarranged subsequent to a second D-flipflop unit 80 having a resetfacility, whose clock input 80 c is connected to the output of thedecision unit 60.

[0026] The signal is enabled by an AND circuit 90 arranged subsequent tothe shift register 30 and the second D-flipflop unit 80, which ANDcircuit has its first input connected to the output of the shiftregister 30 and its second input connected to the output of the secondD-flipflop unit 80, and whose output can supply the signal for furtherprocessing when the signal state pattern picked up by the shift register30 and possibly also completely inverted corresponds to thepredetermined state pattern.

[0027] For a concrete realization of the synchronization process, theclock recovery unit 50 is particularly constituted as a dual counterhaving a length n, which is controlled by means of the clock signal andat which the frequency of the clock signal is a factor of 2^(n+1) largerthan the frequency of the signal itself (however, according to theinvention, it is alternatively possible to set the frequency of theclock signal to an arbitrary different value than the 2^(n+1)-fold valueof the signal). Upon every overflow of the clock recovery unit 50, aslope is generated at its output (for completeness' sake it is to benoted that the invention also provides the possibility of a take-over ofthe signal in the shift register 30 also at instants other than theinstant of the counter overflow).

[0028] A slope occurring in the signal now resets the count of the clockrecovery unit 50 to the value 2^(n−1)−1 (cf. FIG. 3). In accordance withan optional embodiment of the circuit arrangement 100 it is alsopossible to reset the count of the clock recovery unit 50 to a valuewhich is not equal to 2^(n−1)−1 when there is a slope in the signal,which value can be computed, for example, by means of averaging inaccordance with the digital signal theory, so that the clock recoveryunit 50 is synchronized with the signal (for synchronization of theclock recovery unit 50, the invention also provides the possibility ofevaluating only slope information, i.e. a positive slope or a negativeslope) and any jitter or duty cycle can be compensated in the signalwith deviations which are smaller than one fourth of a bit period (cf.FIG. 3). This also compensates deviations between the bit rate of thesignal and the clock signal.

[0029] List of Reference Signs

[0030]100 circuit arrangement

[0031]10 demodulator unit

[0032]20 first D(elay)-flipflop unit

[0033]20 c clock input of the first D-flipflop unit 20

[0034]20 d D input of the first D-flipflop unit 20

[0035]30 shift register

[0036]30 c clock input of the shift register 30

[0037]40 slope detector

[0038]50 clock recovery unit

[0039]60 decision unit

[0040]70 pattern memory

[0041]80 second D-flipflop unit

[0042]80 c clock input of the second D-flipflop unit 80

[0043]90 AND circuit

[0044]200 controller unit

1. A method of detecting synchronization patterns in a receiver,particularly a UHF receiver or a VHF receiver, the method comprising thefollowing successive and/or simultaneous steps: (a) synchronizing atleast a clock recovery unit (50) with an incoming signal; (b.1)impressing, particularly successively impressing at least a shiftregister (30) with the signal, (b.2) generating slopes from the signalby means of at least a slope detector (40) and/or by means of the clockrecovery unit (50) preceded by the slope detector (40), and (b.3)picking up or taking over the slope-determined instantaneous state ofthe signal in the shift register (30); (c) comparing, particularlycontinuously comparing the state pattern assumed by the shift register(30) with a predetermined state pattern stored in at least a patternmemory (70); (d) enabling the signal for the further processingparticularly in at least a controller unit (200) when the state patternassumed by the shift register (30) and possibly also completely invertedcorresponds to the predetermined state pattern.
 2. A method as claimedin claim 1, characterized in that the signal is demodulated beforesynchronization by means of at least a demodulator unit (10).
 3. Amethod as claimed in claim 1 or 2, characterized in that the clockrecovery unit (50) is controlled by means of a clock signal having afrequency which is higher than the frequency of the signal.
 4. A methodas claimed in any one of claims 1 to 3, characterized in that only thenegative slope information and/or only the positive slope information isevaluated for synchronizing the clock recovery unit (50).
 5. A method asclaimed in any one of claims 1 to 4, characterized in that, upon eachoverflow of the clock recovery unit (50), a slope is generated at theoutput of the clock recovery unit (50) and/or the signal is taken overin the shift register (30).
 6. A method as claimed in any one of claims1 to 5, characterized in that the clock recovery unit (50) is reset tothe value 2^(n−1)−1 by a slope in the incoming signal.
 7. A method asclaimed in any one of claims 1 to 5, characterized in that, by a slopein the incoming signal, the clock recovery unit (50) is reset to a valuecomputed by way of averaging in accordance with the digital signaltheory.
 8. A method as claimed in any one of claims 1 to 7,characterized in that the state pattern taken up by the shift register(30) is compared with the predetermined state pattern in at least adecision unit (60).
 9. A method as claimed in any one of claims 1 to 8,characterized in that the data clock generated by the clock recoveryunit (50) is also further processed in the controller unit (200).
 10. Amethod as claimed in claim 9, characterized in that the data clockgenerated by the clock recovery unit (50) is not applied to the outputof the circuit arrangement (100) until after the state pattern of thesignal corresponds to the predetermined state pattern.
 11. A circuitarrangement (100) for detecting synchronization patterns in a receiver,particularly a UHF receiver or a VHF receiver, the circuit arrangementcomprising at least a shift register (30) whose input can be impressedwith an incoming signal and which is provided for picking up or takingover the signal state pattern particularly determined by the slopes; atleast a slope detector (40) whose input can also be impressed with theincoming signal; at least a clock recovery unit (50) to be synchronizedwith the signal and preceded by the slope detector (40), the output ofsaid clock recovery unit being connected to the clock input (30 c) ofthe shift register (30); and at least a decision unit (60) preceded bythe shift register (30) for comparing, particularly continuouslycomparing the signal state pattern picked up by the shift register (30)and possibly also completely inverted with a predetermined state patternstored in at least a pattern memory (70) assigned to the decision unit(60).
 12. A circuit arrangement (100) as claimed in claim 11,characterized in that both the shift register (30) and the slopedetector (40) are preceded by at least a first D(elay)-flipflop unit(20).
 13. A circuit arrangement (100) as claimed in claim 12,characterized in that the D input (20 d) of the first D-flipflop unit(20) is preceded by at least a demodulator unit (10), and the D input(20 d) of the first D-flipflop unit (20) can be impressed with thesignal.
 14. A circuit arrangement (100) as claimed in claim 12 or 13,characterized in that both the clock input (20 c) of the firstD-flipflop unit (20) and the input of the clock recovery unit (50) canbe impressed with a clock signal.
 15. A circuit arrangement (100) asclaimed in claim 14, characterized in that the frequency of the clocksignal is larger by a factor of 2^(n+1) than the frequency of thesignal, in which n is the length of the clock recovery unit (50).
 16. Acircuit arrangement (100) as claimed in any one of claims 11 to 15,characterized in that the clock recovery unit (50) is formed as at leasta dual counter.
 17. A circuit arrangement (100) as claimed in any one ofclaims 11 to 16, characterized in that the slope detector (40) and/orthe clock recovery unit (50) are provided for generating slopes from thesignal.
 18. A circuit arrangement (100) as claimed in any one of claims11 to 17, characterized in that the overall depth of the pattern memory(70) is larger by a factor of 2 than the number of bits of thesynchronization pattern.
 19. A circuit arrangement (100) as claimed inany one of claims 11 to 18, characterized in that the decision unit (60)precedes at least a second D-flipflop unit (80) whose clock input (80 c)is connected to the output of the decision unit (60).
 20. A circuitarrangement (100) as claimed in claim 19, characterized in that theshift register (30) and the second D-flipflop unit (80) precede at leastan AND circuit (90), having a first input which is connected to theoutput of the shift register (30), a second input which is connected tothe output of the second D-flipflop unit (80), and an output which cansupply the signal for further processing particularly in at least acontroller unit (20) when the signal state pattern picked up by theshift register (30) and possibly also completely inverted corresponds tothe predetermined state pattern.
 21. A circuit arrangement (100) asclaimed in claim 20, characterized in that the controller unit (200) canbe impressed with the data clock generated by the clock recovery unit(50).
 22. A circuit arrangement (100) as claimed in any one of claims 11to 21, characterized in that the length of the shift register (30) isdetermined by the length of the signal state pattern to be detected. 23.An integrated circuit, particularly a controller unit (200), controlledby at least a circuit arrangement (100) as claimed in any one of claims11 to 22.